1. Field of the Invention
This invention relates generally to electronic circuits for controlling input data signals to binary data-storage devices and more particularly to circuits which protect such devices from excessive voltage excursions in the input data signals.
2. Description of the Prior Art
Within the prior art, access to a binary data storage device is typically controlled through a transistor which is turned on to access the device and is turned off for isolating the device.
Referring to the drawings, FIG. 1 shows a prior art arrangement for accessing a typical binary data-storage device 10 comprising a storage capacitor C1 to ground coupled through an input line conductor 12 at a node A to the gate electrode G1 of an enhancement-mode N-channel metal-oxide semiconductor (MOS) field-effect transistor Q1 having a first source-drain electrode DS1 coupled to output terminal 14 and having a second source-drain electrode SD1 coupled to terminal 15; in one example, terminal 15 is connected to ground. Capacitor C1 may simply be the parasitic input capacitance associated with input line 12. According to the conventional definition, device 10 is in the low logic or binary "0" state when capacitor C1 is not charged (or is substantially discharged) and is in the high logic or binary "1" state when capacitor C1 is charged to a prescribed level.
Device 10 is accessed along input line 12 through an enhancement-mode N-channel MOS field-effect transistor Q2 having a first source-drain electrode SD2 coupled through a signal-carrying conductor 16 to an input data terminal 18 and having a second source-drain electrode DS2 connected to input line 12 as shown in FIG. 1. An input data signal V.sub.IN is applied at input data terminal 18 for transferring a binary data bit comprising either a "0" when data signal V.sub.IN is at a binary low voltage or a "1" when data signal V.sub.IN is at a binary high voltage through transistor Q2 into device 10. The gate electrode G2 of transistor Q2 is coupled to an input control terminal 20 at which an input control signal .phi. is applied to control the conducting/non-conducting operation of transistor Q2. When control signal .phi. is at a binary logical high voltage--i.e., a positive voltage exceeding the threshold voltage of transistor Q2--data signal V.sub.IN is written into device 10. Switching control signal .phi. to a binary logical low voltage--i.e., a voltage below the threshold voltage of transistor Q2--is intended to turn off transistor Q2 and thereby to isolate or disconnect device 10 from input data terminal 18 and data signal V.sub.IN.
As long as data signal V.sub.IN is at or above its binary low voltage, there is substantially no change in the state of device 10 due to changes in data signal V.sub.IN when control signal .phi. is at its logical low voltage. However, noise or other activities in the circuitry preceding input data terminal 18 often causes data signal V.sub.IN to undershoot below its binary low voltage. If the magnitude of this negative undershoot in data signal V.sub.IN exceeds the threshold voltage of transistor Q2, it then turns on. A "1" stored in capacitor C1 then discharges through transistor Q2 and is degraded or destroyed.
FIGS. 2 and 3 illustrate two prior art arrangements utilized to reduce sensitivity to a negative voltage undershoot in data signal V.sub.IN.
The circuitry of FIG. 1 is modified in FIG. 2 by including another enhancement-mode N-channel MOS field-effect transistor Q3 between input data terminal 18 and device 10. Transistor Q3 has its gate electrode G3 connected to input control terminal 20 to receive control signal .phi., a first source-drain electrode SD3 coupled through a node B to source-drain electrode DS2 of transistor Q2, and a second source-drain electrode DS3 connected to node A. Node B is coupled through an RC network comprising a capacitor C2 and a resistor R1 to a positive voltage source V.sub.DD. Capacitor C2 discharges when data signal V.sub.IN is at a low voltage level. This serves to reduce the transitory rate at which the voltage changes at node A. However, the RC network provides little protection against a sustained negative input undershoot in data signal V.sub.IN.
The prior art circuit of FIG. 3 utilizes transistor Q3 connected as described for FIG. 2. However, instead of the RC network, an enhancement-mode N-channel MOS field-effect transistor Q4 is coupled by its source S4 to node B. The drain D4 and the gate G4 of transistor Q4 are coupled to each other and to a substrate supply voltage source V.sub.SS which is typically at ground potential. Similarly, another enhancement-mode N-channel MOS transistor Q5 is coupled through its source S5 to signal-carrying conductor 16. The drain D5 and gate G5 of transistor Q5 are connected to each other and likewise to voltage source V.sub.SS. When data signal V.sub.IN drops to a negative value whose magnitude exceeds the threshold voltage of transistor Q2, current is provided through diode-connected transistors Q4 and Q5 from voltage source V.sub.SS as well as from node A. By proper sizing of transistors Q4 and Q5, the voltage loss at node B may transiently be significantly decreased and the degradation of a "1" in device 10 due to spike negative voltage undershoot in data signal V.sub.IN is reduced. As with the circuit shown in FIG. 2, the circuit of FIG. 3 provides little protection against a sustained negative input undershoot.